Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
xr XRK39653
3.3V, 8-OUTPUT ZERO DELAY BUFFER
NOVEMBER 2006 REV. 1.0.0
XRK39653 GENERAL DESCRIPTION
The XRK39653 is a low voltage high perfor m ance PLL
based zero delay buffer/clock generator designed for high
speed clock dist ri bution applications. It provides 9 low
skew, low jitter outputs ideal for n etworking, compu ting and
telecom applications.
The PLL bas ed des ign al lows th e 9 out puts (8 cloc k output s
and 1 feedback output) to be phase aligned to t he input ref
-
erence clock. The outputs source LVCM OS compatible lev-
els and can drive 50Ω trans mission li nes. If seri es
terminati on is used, each output can dri ve up to 2 lines pro
-
vidi ng effectively a fanout of 1:16. The XRK39653’s refer-
ence input accepts a LVPECL clock source.
For normal operation (PLL used to source the outputs), the
feedback output (QFB) is connected to the feedback input
(FB_IN). The VCO range of ope rat ion is 200 to 500MHz.
This means that the i nput/output ranges are determined by
the di vider se ttin g. If ÷ 4 is used , t he inpu t/out put ran ge i s 50
to 125 MHz (hi gh rang e), i f ÷ 8 i s used t he input /outp ut range
is 25 to 62.5MHz (l ow range).
For testing purposes tw o PLL bypass mo des are p rovided.
The first simp ly r eplaces the PLL output with the reference
clock (PLL_EN=0,
BYPASS=1). The di viders are st ill in
use. The second is a full bypass mode that has the PLL
and divi der operation removed (
BYPASS=0). In this mode
the reference clock directly sou rces the outputs dri vers.
FEATURES
• 8 LVCMOS Clock Outputs
• 1 Feedbac k Output
• LVPECL reference clock input
• 25-125 MHz input/output frequency range
■ Input/Output range (÷4): 50-125MHz
■ Input/Output range (÷8): 25-62.5MHz
• 150ps max output to output skew
• Two by pass test mode option s
• Fully Integrated PLL
• 3.3V Operation
• Pin compatible with MPC965 3
• Industrial temp range: -40°C to +85°C
• 32-Lead TQFP Packaging
FIGURE 1. BLOCK DIAGRAM OF THE XRK39653
PLL
Ref
FB
1
0
1
0
1
0
FB_IN
PLL_EN
OE
PECL
PEC L
Q5
Q6
Q7
QF
2÷
4÷
Q4
Q0
Q1
Q2
Q3
CO_SEL
BYPASS
VDD
VDD
